Self aligned architectures in bipolar transistors are advantageous is that they provide better window downscaling and lower levels of parasitic capacitances and parasitic resistances. One commonly used prior art method of manufacturing self aligned bipolar transistors involves the use of a sacrificial nitride emitter. Chemical mechanical polishing (CMP) processes are often required to planarize the top of the sacrificial nitride emitter. For example, consider the prior art method for manufacturing a bipolar transistor shown in FIG. 1 and in FIG. 2.
FIG. 1 illustrates a schematic diagram 100 of a cross section of an intermediate structure formed during the manufacture of a prior art bipolar transistor showing a thick dielectric layer placed over a sacrificial nitride emitter. The intermediate structure shown in FIG. 1 comprises a Non-Selective Epitaxial Growth (NSEG) collector 110 and a selective implanted collector (SIC) 120 located within a central portion of the NSEG collector 110. The central portion of the NSEG collector 110 is located between two shallow trench isolation (STI) structures 130. As shown in FIG. 1, a layer of Non-Selective Epitaxial Growth (NSEG) base material 140 is placed over the NSEG collector 110 and over the STI structures 130.
Then a layer of a silicon oxide material 150 is placed over the NSEG base 140. Then a layer of silicon nitride 160 is placed over the silicon oxide material 150 to form a sacrificial nitride emitter. Then non-central portions of the layer of silicon nitride 160 are removed. Portions of the silicon oxide material 150 that are not located under the central portion of the silicon nitride 160 are also removed. The resulting structure of the silicon oxide material 150 and the resulting structure of the silicon nitride 160 are shown in FIG. 1.
Then a layer of silicon/polysilicon 170 is placed over the NSEG base material 140. Then a relatively thick layer of oxide (e.g. tetraethyloxysilane) 180 is placed over the silicon nitride 160 and over the silicon/polysilicon layer 170.
Then a chemical mechanical polishing (CMP) procedure is applied to expose the top of the sacrificial nitride emitter 160. FIG. 2 illustrates a schematic diagram 200 of a cross section of the intermediate structure 100 shown in FIG. 1 following the application of the chemical mechanical polishing (CMP) procedure. The chemical mechanical polishing (CMP) procedure has removed the portions of the oxide layer 180 from the top of the sacrificial nitride emitter 160. The exposed top of the sacrificial nitride emitter 160 is designated with reference numeral 210 in FIG. 2.
The required prior art step of applying a chemical mechanical polishing (CMP) procedure imposes a high level of process complexity in the manufacture of bipolar transistors. The required prior art step of applying a chemical mechanical polishing (CMP) procedure also limits the reproducibility of the process for more advanced emitter geometry.
When this type of self aligned architecture for a bipolar transistor (that requires the use of a CMP procedure) is integrated into a Bipolar-Complementary Metal Oxide Semiconductor (BiCMOS) technology, the CMP step presents a major problem for compatibility. This is due to the fact that using the CMP step requires precise control in order to avoid damaging the CMOS polysilicon gate region.
Therefore, there is a need in the art for a system and method that is capable of solving the problems that occur when such prior art methods are utilized. In particular, there is a need in the art for a system and method for providing an efficient process that is capable of manufacturing a self aligned bipolar transistor using a simplified sacrificial nitride emitter.
The method of the present invention solves the problems that are associated with the prior art by providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor. Then a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process. The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter. The sacrificial emitter is then etched away to form an emitter window. Then a polysilicon emitter structure is formed in the emitter window. The self aligned bipolar transistor architecture of the invention is completely compatible with BiCMOS technology.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.